1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device having a three-dimensional structure where a plurality of memory cells are stacked vertically from a substrate, and a method for fabricating the non-volatile memory device.
2. Description of the Related Art
Non-volatile memory devices retain data although power is turned off. Currently, various nonvolatile memory devices, such as a flash memory, have been widely used.
As the integration degree of a non-volatile memory device having a two-dimensional structure where memory cells are formed in a single layer may reach a limit, a non-volatile memory device having a three-dimensional structure where a plurality of memory cells are formed along the channels that are extend vertically from a semiconductor substrate have been suggested. More specifically, non-volatile memory devices having a three-dimensional structure are divided into devices having a linear channel layers and devices having U-shaped channel layers.
A charge-trapping-type non-volatile memory device generally includes a memory layer between a channel layer and a gate electrode, and the memory layer includes a charge blocking layer, a charge storage layer, and a channel insulation layer. However, erase operation characteristics of a charge-trapping-type non-volatile memory device are deteriorated due to back tunneling that occurs as the electrons are introduced to the charge storage layer through the charge blocking layer when a memory cell performs an erase operation.
To address this back tunneling, a method of forming the charge blocking layer thick or a method of using a high dielectric layer is suggested. However, preventing the charges from being introduced from the charge blocking layer to the charge storage layer may be difficult, and the size of the non-volatile memory device may be increased.